Simulation and Synthesis Techniques for Asynchronous FIFO Design

作者：Clifford E. Cummings，Sunburst Design，Inc，Cliffc@sunburst-design.com

今天對跨時鐘域FIFO設計領域的經典論文進行雙語研讀，力求還原原汁原味。 

摘要

An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each other.Asynchronous FIFOs are used to safely pass data from one clock domain to another clock domain.

異步 FIFO 是指一種 FIFO 類型，數據從一個時鐘域寫入 FIFO Buffer并從同一 FIFO Buffer的另一個時鐘域中讀出，這兩個時鐘域是異步的。異步 FIFO 被用于安全地對數據進行跨時鐘域傳輸。

There are many ways to do asynchronous FIFO design, including many wrong ways. Most incorrectly implemented FIFO designs still function properly 90% of the time. Most almost-correct FIFO designs function properly 99%+ of the time. Unfortunately, FIFOs that work properly 99%+ of the time have design flaws that are usually the most difficult to detect and debug (if you are lucky enough to notice the bug before shipping the product), or the most costly to diagnose and recall (if the bug is not discovered until the product is in the hands of a dissatisfied customer).

異步 FIFO 的設計方法有很多種，其中包括許多錯誤的方法。大多數實現不正確的 FIFO 設計仍然有 90% 的時間正常工作。大多數幾乎正確（almost-correct）的 FIFO 設計有 99% 以上的時間正常工作。不幸的是，在 99% 以上的時間里正常工作的 FIFO 中的設計缺陷通常是最難檢測和調試的 (如果你足夠幸運，在發布產品之前發現了 bug)、或者診斷和召回成本最高的 (如果直到產品到達不滿意的客戶手中才發現 bug)。

This paper discusses one FIFO design style and important details that must be considered when doing asynchronous FIFO design.The rest of the paper simply refers to an “asynchronous FIFO” as just “FIFO.”

本文討論了一種 FIFO 設計風格，以及在進行異步 FIFO 設計時必須考慮的重要細節。文章的其余部分只是簡單地將 “異步 FIFO” 稱為 “FIFO”。 

2.0 傳遞多個異步信號(Passing multiple asynchronous signals)

Attempting to synchronize multiple changing signals from one clock domain into a new clock domain and insuring that all changing signals are synchronized to the same clock cycle in the new clock domain has been shown to be problematic^[1]. FIFOs are used in designs to safely pass multi-bit data words from one clock domain to another. Data words are placed into a FIFO buffer memory array by control signals in one clock domain, and the data words are removed from another port of the same FIFO buffer memory array by control signals from a second clock domain. Conceptually, the task of designing a FIFO with these assumptions seems to be easy.

試圖將多位變化信號從一個時鐘域同步到一個新的時鐘域，并確保所有變化信號在新的時鐘域中同步到相同的時鐘周期是一個難題 ^[1]。安全地將多位數據字從一個時鐘域傳遞到另一個時鐘域需要用到FIFO。數據字(Data Words)通過時鐘域“A”中的控制信號放置在 FIFO Buffer的存儲器陣列（Memory  Array）中，并通過另一個時鐘域“B”的控制信號從同一 FIFO Buffer存儲器陣列的另一個端口中移除。從概念上來說，設計一個具有這些假設的 FIFO 的任務似乎很容易。

The difficulty associated with doing FIFO design is related to generating the FIFO pointers and finding a reliable way to determine full and empty status on the FIFO.

難點在于生成 FIFO 指針并找到一種可靠的方法來確定 FIFO 的空、滿狀態。

2.1 同步 FIFO 指針(Synchronous FIFO pointers)

For synchronous FIFO design (a FIFO where writes to, and reads from the FIFO buffer are conducted in the same clock domain), one implementation counts the number of writes to, and reads from the FIFO buffer to increment (on FIFO write but no read), decrement (on FIFO read but no write) or hold (no writes and reads, or simultaneous write and read operation) the current fill value of the FIFO buffer. The FIFO is full when the FIFO counter reaches a predetermined full value and the FIFO is empty when the FIFO counter is zero.

同步 FIFO 設計 (讀寫 FIFO 都在同一時鐘域中進行)需要實現讀寫 FIFO 的計數，其操作包括增加 (只寫不讀)、減少 (只讀取不寫) 或保持 (不讀寫，或同時進行讀寫操作) FIFO Buffer中的內容。當 FIFO 計數器達到預定義的滿（full）值時，FIFO 為滿；當 FIFO 計數器為零時，FIFO 為空。

Unfortunately, for asynchronous FIFO design, the increment-decrement FIFO fill counter cannot be used, because two different and asynchronous clocks would be required to control the counter. To determine full and empty status for an asynchronous FIFO design, the write and read pointers will have to be compared.

遺憾的是，對于異步 FIFO 設計，不能使用增 - 減 FIFO 計數器，因為需要兩個不同的異步時鐘來控制它。為了確定異步 FIFO 設計的滿狀態和空狀態，必須比較寫入和讀取指針。

2.2 異步 FIFO 指針（Asynchronous FIFO pointer）

In order to understand FIFO design, one needs to understand how the FIFO pointers work. The write pointer always points to the next word to be written; therefore, on reset, both pointers are set to zero, which also happens to be the next FIFO word location to be written. On a FIFO-write operation, the memory location that is pointed to by the write pointer is written, and then the write pointer is incremented to point to the next location to be written.

為了理解 FIFO 設計，我們需要理解 FIFO 指針的工作原理。write 指針始終指向下一個要寫入的字，在Reset時兩個指針都會設置為 0，這恰好也是下一個要寫入的 FIFO字的位置。在 FIFO 寫入操作中，write 指針指向的內存位置被寫入，然后 write 指針被遞增指向下一個要寫入的位置。

Similarly, the read pointer always points to the current FIFO word to be read. Again on reset, both pointers are reset to zero, the FIFO is empty and the read pointer is pointing to invalid data (because the FIFO is empty and the empty flag is asserted). As soon as the first data word is written to the FIFO, the write pointer increments, the empty flag is cleared, and the read pointer that is still addressing the contents of the first FIFO memory word, immediately drives that first valid word onto the FIFO data output port, to be read by the receiver logic. The fact that the read pointer is always pointing to the next FIFO word to be read means that the receiver logic does not have to use two clock periods to read the data word. If the receiver first had to increment the read pointer before reading a FIFO data word, the receiver would clock once to output the data word from the FIFO, and clock a second time to capture the data word into the receiver. That would be needlessly inefficient.

同樣，read 指針始終指向當前要讀取的字。在Reset時兩個指針都重置為 0，FIFO 為空，read 指針指向無效數據 (因為 FIFO 為空，并且empty flas is asserted)。一旦第一字被寫入 FIFO, write指針就會增加，空標志會被清除，而仍在處理第一個 FIFO 字的 read 指針會立即將該（第一個）有效字驅動到 FIFO 的數據輸出端口，以便由接收器邏輯讀取。read 指針始終指向下一個要讀取的 FIFO Word意味著接收器邏輯不必使用兩個時鐘周期來讀取數據字。如果接收器在讀取 FIFO 數據之前必須先增加 read 指針，在這種情況下，接收器將計數一次以輸出 FIFO 中的Word，然后計數第二次以將該Word捕獲到接收器中，這將帶來不必要的低效。

The FIFO is empty when the read and write pointers are both equal. This condition happens when both pointers are reset to zero during a reset operation, or when the read pointer catches up to the write pointer, having read the last word from the FIFO.A FIFO is full when the pointers are again equal, that is, when the write pointer has wrapped around and caught up to the read pointer. This is a problem. The FIFO is either empty or full when the pointers are equal, but which?

當read指針和write指針都相等時，FIFO 為空。這種情況發生在兩個指針都被重置為零時，或者當read指針讀取 FIFO 的最后一個詞后趕上write指針時。當指針再次相等時，即write指針繞過并追上read指針時，FIFO 就是滿的。這里引出一個問題，當指針相等時，FIFO 要么是空的，要么是滿的，但究竟是哪種情況呢？

One design technique used to distinguish between full and empty is to add an extra bit to each pointer. When the write pointer increments past the final FIFO address, the write pointer will increment the unused MSB while setting the rest of the bits back to zero as shown in Figure 1 (the FIFO has wrapped and toggled the pointer MSB). The same is done with the read pointer. If the MSBs of the two pointers are different, it means that the write pointer has wrapped one more time that the read pointer. If the MSBs of the two pointers are the same, it means that both pointers have wrapped the same number of times.

用于區分滿指針和空指針的一種設計技術是為每個指針添加一個額外的位。當write指針的增量超過最終 FIFO 地址時，write指針會增加未使用的 MSB（最高位）同時將其余位重置為零，如圖 1 所示 。read指針也是如此。如果兩個指針的 MSB 不同，這意味著寫指針比讀指針多跑了一輪。兩個指針的 MSB 相同則意味著兩個指針在同一輪中。

 圖1.異步FIFO的空滿條件

Using n -bit pointers where (n-1) is the number of address bits required to access the entire FIFO memory buffer, the FIFO is empty when both pointers, including the MSBs are equal. And the FIFO is full when both pointers, except the MSBs are equal.The FIFO design in this paper uses n-bit pointers for a FIFO with 2 ^(n-1) write-able locations to help handle full and empty conditions. More design details related to the full and empty logic are included in section 5.0.

使用 n 位指針，其中 (n-1) 位是訪問整個 FIFO 內存緩沖區所需的地址位數，當兩個指針 (包括 MSB) 相等時，FIFO 為空。當兩個指針 (包括 MSB) 都相等時，FIFO 為滿。為了處理空滿條件，本文中的 FIFO 設計使用 n 位指針來處理具有 2 ^(n-1) 個可寫位置的 FIFO。更多與空滿邏輯相關的設計細節請參見 5.0 節。

2.3 二進制 FIFO 指針注意事項（Binary FIFO pointer considerations）

Trying to synchronize a binary count value from one clock domain to another is problematic because every bit of an n-bit counter can change simultaneously (example 7- >8 in binary numbers is 0111->1000, all bits changed). One approach to the problem is sample and hold periodic binary count values in a holding register and pass a synchronized ready signal to the new clock domain. When the ready signal is recognized, the receiving clock domain sends back a synchronized acknowledge signal to the sending clock domain. A sampled pointer must not change until an acknowledge signal is received from the receiving clock domain. A count-value with multiple changing bits can be safely transferred to a new clock domain using this technique. Upon receipt of an acknowledge signal, the sending clock domain has permission to clear the ready signal and re-sample the binary count value.

嘗試將以二進制表示的計數值從一個時鐘域同步到另一個時鐘域是有問題的，因為 n 位計數器的每個位都可能同時更改 (例如，二進制數 7->8 是 0111->1000, 所有位都已更改)。【*注：此時就變成了多比特跨時鐘域問題】

解決這個問題的一種方法是采樣并在保持寄存器（holding register）中保存周期性的二進制計數值，然后將同步的ready信號傳遞給新的時鐘域。當識別到ready信號時，接收時鐘域會向發送時鐘域發回同步的確認信號。在接收到來自接收時鐘域的確認信號之前，采樣的指針不得更改。【*注：握手的過程】使用這種技術，可以安全地將具有多個位同時變化的計數值傳輸到新的時鐘域。收到確認信號后，發送時鐘域有權清除ready信號并采樣新的二進制計數值。

Using this technique, the binary counter values are sampled periodically and not all of the binary counter values can be passed to a new clock domain The question is, do we need to be concerned about the case where a binary counter might continue to increment and overflow or underflow the FIFO between sampled counter values? The answer is no^[8].

使用這種技術，二進制計數器值是周期性采樣的，并非所有二進制計數器值都能傳遞到新的時鐘域。問題是，我們是否需要擔心在采樣相鄰的計數器值之間FIFO增加(increment)、溢出(overflow)或反向溢出(underflow)? 答案是否定的 ^[8]。

FIFO full occurs when the write pointer catches up to the synchronized and sampled read pointer. The synchronized and sampled read pointer might not reflect the current value of the actual read pointer but the write pointer will not try to count beyond the synchronized read pointer value. Overflow will not occur^[8].FIFO empty occurs when the read pointer catches up to the synchronized and sampled write pointer. The synchronized and sampled write pointer might not reflect the current value of the actual write pointer but the read pointer will not try to count beyond the synchronized write pointer value. Underflow will not occur[8].More observations about this technique of sampling binary pointers with a synchronized ready-acknowledge pair of handshaking signals are detailed in section 7.0, after the discussion of synchronized Gray^[6] code pointers.

當write指針趕上同步和采樣的read指針時，就會發生 FIFO Full。同步和采樣的read指針可能不會反映實際read指針的當前值，但write指針不會試圖超過同步的read指針值。不會發生溢出 ^[8]。當read指針趕上同步和采樣的write指針時，FIFO 為空。同步和采樣的write指針可能不會反映實際write指針的當前值，但read指針不會試圖超過同步write指針的值進行計數。不會發生下溢 ^[8]。在討論同步 Gray ^[6] 碼指針后的第 7.0 節中，將詳細介紹這種使用同步的準確確認握手信號對對采樣二進制指針的技術。

A common approach to FIFO counter-pointers, is to use Gray code counters. Gray codes only allow one bit to change for each clock transition, eliminating the problem associated with trying to synchronize multiple changing signals on the same clock edge.

FIFO 計數器的一種常用方法是使用Gary碼計數器。Gary碼每次時鐘沿只允許改變一位，消除了試圖在同一時鐘沿同步多個變化信號的問題。

2.4 FIFO 測試問題（FIFO testing troubles）

Testing a FIFO design for subtle design problems is nearly impossible to do. The problem is rooted in the fact that FIFO pointers in an RTL simulation behave ideally, even though, if incorrectly implemented, they can cause catastrophic failures if used in a real design.

測試 FIFO 設計中的微妙設計問題幾乎是不可能的。問題的根源在于盡管 RTL 仿真中的 FIFO 指針表現理想，但如果實現不當，它們在實際設計中可能會導致災難性的故障。

In an RTL simulation, if binary-count FIFO pointers are included in the design all of the FIFO pointer bits will change simultaneously; there is no chance to observe synchronization and comparison problems. In a gate-level simulation with no backannotated delays, there is only a slight chance of observing a problem if the gate transitions are different for rising and falling edge signals, and even then, one would have to get lucky and have the correct sequence of bits changing just prior to and just after a rising clock edge. For higher speed designs, the delay differences between rising and falling edge signals diminishes and the probability of detecting problems also diminishes. Finding actual FIFO design problems is greatest for gate-level designs with backannotated delays, but even doing this type of simulation, finding problems will be difficult to do and again the odds of observing the design problems decreases as signal propagation delays diminish.

在 RTL 仿真中，如果設計中包含二進制計數的 FIFO 指針，所有 FIFO 指針位將同時變化；沒有機會觀察到同步和比較問題。在沒有反標延遲的門級仿真中，如果上升和下降沿信號的門延遲（gate transition）不同，觀察到問題的機會很小。即使二者相同，在上升時鐘沿之前和之后發生正確的位序列變化也是在碰運氣。對于更高速度的設計，上升和下降沿信號之間的延遲差異減小，檢測到問題的概率也隨之降低。在具有反標延遲的門級設計中找到實際的 FIFO 設計問題是最有可能的，但即使進行這種類型的仿真，找到問題也將很困難，而且隨著信號傳播延遲的減小，觀察到設計問題的概率也會降低。

Clearly the answer is to recognize that there are potential FIFO design problems and to do the design correctly from the start.

顯然，答案是承認存在潛在的 FIFO 設計問題，并從一開始就正確地進行設計。

The behavioral model that I sometimes use for testing a FIFO design is a FIFO model that is simple to code, is accurate for behavioral testing purposes and would be difficult to debug if it were used as an RTL synthesis model. This FIFO model is only recommended for use in a FIFO testbench. The model accurately determines when FIFO full and empty status bits should be set and can be used to determine the data values that should have been stored into a working FIFO. THIS FIFO MODEL IS NOT SAFE FOR SYNTHESIS!

我有時會用下述的 FIFO 模型測試FIFO設計，它編碼簡單且對行為級測試目標而言是準確的，但如果用作 RTL 綜合模型，調試將會很困難。這個 FIFO 模型僅推薦在 FIFO Teshbench中使用，它準確地確定應該何時設置 FIFO 的空滿狀態位，并且決定如何存儲工作 FIFO 中的數據值。【千萬不要將該 FIFO 模型用于綜合！】

 1 module beh_fifo (rdata, wfull, rempty, wdata,
 2 winc, wclk, wrst_n, rinc, rclk, rrst_n);
 3     parameter DSIZE = 8;
 4     parameter ASIZE = 4;
 5     output [DSIZE-1:0] rdata;
 6     output wfull;
 7     output rempty;
 8     input [DSIZE-1:0] wdata;
 9     input winc, wclk, wrst_n;
10     input rinc, rclk, rrst_n;
11     reg [ASIZE:0] wptr, wrptr1, wrptr2, wrptr3;
12     reg [ASIZE:0] rptr, rwptr1, rwptr2, rwptr3;
13     parameter MEMDEPTH = 1<<ASIZE;
14     reg [DSIZE-1:0] ex_mem [0:MEMDEPTH-1];
15     always @(posedge wclk or negedge wrst_n)
16         if (!wrst_n) wptr <= 0;
17         else if (winc && !wfull) begin
18             ex_mem[wptr[ASIZE-1:0]] <= wdata;
19             wptr <= wptr+1;
20         end
21     always @(posedge wclk or negedge wrst_n)
22         if (!wrst_n) {wrptr3,wrptr2,wrptr1} <= 0;
23         else {wrptr3,wrptr2,wrptr1} <= {wrptr2,wrptr1,rptr};
24     always @(posedge rclk or negedge rrst_n)
25         if (!rrst_n) rptr <= 0;
26         else if (rinc && !rempty) rptr <= rptr+1;
27     always @(posedge rclk or negedge rrst_n)
28         if (!rrst_n) {rwptr3,rwptr2,rwptr1} <= 0;
29     else {rwptr3,rwptr2,rwptr1} <= {rwptr2,rwptr1,wptr};
30     assign rdata = ex_mem[rptr[ASIZE-1:0]];
31     assign rempty = (rptr == rwptr3);
32     assign wfull = ((wptr[ASIZE-1:0] == wrptr3[ASIZE-1:0]) &&
33     (wptr[ASIZE] != wrptr3[ASIZE] ));
34 endmodule         

Example 1.僅測試使用的FIFO行為級模型

In the behavioral model of Example 1, it is okay to use binary-count pointers, a Verilog array to represent the FIFO memory buffer, multi-asynchronous clocks in the same module and non-registered outputs. THIS MODEL IS NOT INTENDED FOR SYNTHESIS! (Hopefully enough capital letters have been used in this section to discourage anyone from trying to synthesize this model!)

在例 1 的行為模型中，使用二進制計數指針、表示 FIFO 內存緩沖區的 Verilog 數組、同一模塊中的多個異步時鐘和非寄存器輸出都是可以的。這個模型不可于 Synthesis ！(希望本節中使用的大寫字母足夠多，以阻止任何人嘗試綜合這個模型！)

Two of the always blocks in the module (the always blocks with concatenations) are included to behaviorally represent the synchronization that will be required in the actual RTL FIFO design. They are not important to the testing of the data transfer through the FIFO, but they are important to the testing of the correctly timed full and empty flags in the FIFO model. The exact number of synchronization stages required in the behavioral model is FIFO-design dependent. This model can be used to help test the FIFO design described in this paper.

模塊中的兩個 always 塊 (具有連接的 always 塊) 被包含在內，以行為級的方式表示實際 RTL FIFO 設計中所需的同步。它們對于測試通過 FIFO 的數據傳輸并不重要，但對于測試 FIFO 模型中正確計數的空滿標志很重要。該模型中所需同步階段（synchronization stages）的確切數量取決于 FIFO 設計。該模型可用于幫助測試本文中描述的 FIFO 設計。

 3.0 格雷碼計數器1（Gray code counter-Sytle1）

Gray codes are named for the person who originally patented the code back in 1953, Frank Gray^[6]. There are multiple ways to design a Gray code counter. This section details a simple and straight forward method to do the design. The technique described in this paper uses just one set of flip-flops for the Gray code counter. A second method that uses two sets of flip-flops to achieve higher speeds is detailed in shown in section 4.0.

Gray 碼是以 1953 年最初為該代碼申請專利的人 Frank Gray ^[6] 命名的。設計 Gray 代碼計數器有多種方法，本節詳細介紹了一種簡單直接的設計方法。本文描述的技術只使用了 Gray 碼計數器的一組觸發器。第二種方法是使用兩組觸發器來實現更高的速度，詳見 4.0 節。

注：格雷碼是一種可靠性編碼，任意兩個相鄰的代碼只有一位二進制數不同，其轉換過程可以通過將二進制數與其右移一位的數進行異或運算(XOR)來實現。

3.1 格雷碼模式(Gray code patterns)

For reasons that will be described later, it is desirable to create both an n-bit Gray code counter and an (n- 1)-bit Gray code counter. It would certainly be easy to create the two counters separately, but it is also easy and efficient to create a common n -bit Gray code counter and then modify the 2^nd MSB to form an (n-1)-bit Gray code counter with shared LSBs. In this paper, this will be called a “dual n-bit Gray code counter.”

由于后面將描述的原因，建議同時創建一個 n 位 Gray 碼計數器和一個 (n-1) 位 Gray 碼計數器。分別創建這兩個計數器當然很容易，但創建一個共同的 n 位 Gray 代碼計數器，然后修改第二個 MSB 以形成一個具有共享 LSB 的 (n-1) 位 Gray 碼計算器，也同樣簡單高效。在本文中，這將被稱為 “雙 n 位 Gray 碼計數器”。

注：“雙n位計數器”意味著該計數器在計數時，0~3bit可以用于4bit格雷碼計數，0~2bit同時也滿足“任意兩個相鄰的代碼只有一位二進制數不同”

圖2. n 位Gary碼轉換為 (n-1) 位Gary碼

To better understand the problem of converting an n-bit Gray code to an (n-1)-bit Gray code, consider the example of creating a dual 4-bit and 3-bit Gray code counter as shown in Figure 2.

為了更好地理解將 n 位 Gray 碼轉換為 (n-1) 位 Gray 碼的問題，請考慮創建一個雙 4 位和 3 位 Gray 碼計數器的例子，如圖2所示。

The most common Gray code, as shown in Figure 2, is a reflected code where the bits in any column except the MSB are symmetrical about the sequence mid-point^[6]. This means that the second half of the 4-bit Gray code is a mirror image of the first half with the MSB inverted.

最常見的 Gray 碼，如圖 2 所示，是一種"反射"代碼，其中除 MSB 之外的任何列中的比特都圍繞序列中點對稱^[6]。這意味著 4 比特 Gray 碼的后半部分是前半部分的鏡像，而MSB 是相反的。

To convert a 4-bit to a 3-bit Gray code, we do not want the LSBs of the second half of the 4-bit sequence to be a mirror image of the LSBs of the first half, instead we want the LSBs of the second half to repeat the 4-bit LSB-sequence of the first half.

若想將 4 位Gary碼轉換為 3 位Gary碼，我們不希望 4 位序列后半部分的 LSB 成為前半部分 LSB 的鏡像，而是希望后半部分的 LSB 重復前半部分的 4 位 LSB 序列。

Upon closer examination, it is obvious that inverting the second MSB of the second half of the 4-bit Gray code will produce the desired 3-bit Gray code sequence in the three LSBs of the 4-bit sequence. The only other problem is that the 3-bit Gray code with extra MSB is no longer a true Gray code because when the sequence changes from 7 (Gray 0100) to 8 (~Gray 1000) and again from 15 (~Gray 1100) to 0 (Gray 0000), two bits are changing instead of just one bit. A true Gray code only changes one bit between counts.

仔細觀察可以發現，4 位 Gray 碼后半部分的第二個 MSB 反轉將在 4 位序列的三個 LSB 中產生所需的 3 位 Gray 碼序列。唯一的另一個問題是，帶有額外 MSB 的 3 位 Gray 碼不再是真正的 Gray 碼，因為當序列從 7 (Gray 0100) 變為 8 (~Gray 1000), 再從 15 (~Gray 1100) 變為 0 (Gray 0000) 時，變化的是兩位而不是一位。真正的 Gray 碼在計數之間只變化一位。

3.2 Gray 碼計數器基礎（Gray code counter basics）

The first fact to remember about a Gray code is that the code distance between any two adjacent words is just 1 (only one bit can change from one Gray count to the next). The second fact to remember about a Gray code counter is that most useful Gray code counters must have power-of-2 counts in the sequence. It is possible to make a Gray code counter that counts an even number of sequences but conversions to and from these sequences are generally not as simple to do as the standard Gray code. Also note that there are no odd-count-length Gray code sequences so one cannot make a 23-deep Gray code. This means that the technique described in this paper is used to make a FIFO that is 2ⁿ deep.

關于 Gray 碼需要記住的第一個事實是，任何兩個相鄰字之間的代碼距離只有 1 (從一個 Gray 計數到下一個只能改變一位)。關于 Gray 碼計數器需要記住的第二個事實是，大多數有用的 Gray 碼計數器在序列中必須具有 2 的冪次方的計數。可以創建一個計數偶數個序列的 Gray 碼計數器，但在這些序列之間進行轉換通常不像標準 Gray 碼那樣簡單。還要注意，沒有奇數計數長度的 Gray 碼序列，因此無法創建 23 比特深的 Gray 碼。這意味著本文中描述的技術被用來創建深度為2ⁿ 的FIFO。

Figure 3 is a block diagram for a style #1 dual n-bit Gray code counter. The style #1 Gray code counter assumes that the outputs of the register bits are the Gray code value itself (ptr, either wptr or rptr). The Gray code outputs are then passed to a Gray-to-binary converter (bin), which is passed to a conditional binary-value incrementer to generate the next-binary-count-value (bnext), which is passed to a binary-to-Gray converter that generates the next-Gray-count-value (gnext), which is passed to the register inputs. The top half of the Figure 3 block diagram shows the described logic flow while the bottom half shows logic related to the second Gray code counter as described in the next section.

圖 3 是樣式 #1 的雙 n 位 Gray 碼計數器的示意圖。該 Gray 碼計數器假設寄存器位的輸出是 Gray 碼值本身 (ptr、wptr 或 rptr)。然后，Gray 碼輸出被傳遞給 “Gray 碼到二進制碼轉換器” (bin), 該轉換器被傳遞給一個有條件的二進制值自增器以生成下一個二進制計數值 (bnext), 該值又被傳遞給“二進制碼到 Gray碼轉換器”，該轉換器生成下一個 Gray 計數值 (gnext)并傳遞給寄存器輸入。圖 3 的上半部分顯示了所描述的邏輯流程，而下半部分顯示了下一節將描述的與第二個 Gray 碼計數器相關的邏輯。

圖 3 雙 n-bit Gray 代碼計數器

3.3  雙 n-bit Gray 碼計數器（Dual n-bit Gray code counter）

A dual n-bit Gray code counter is a Gray code counter that generates both an n-bit Gray code sequence (described in section 3.2) and an (n-1)-bit Gray code sequence.The (n- 1)-bit Gray code is simply generated by doing an exclusive-or operation on the two MSBs of the n-bit Gray code to generate the MSB for the (n-1)-bit Gray code. This is combined with the (n-2) LSBs of the n-bit Gray code counter to form the (n-1)-bit Gray code counter^[5].

雙 n 位 Gray 代碼計數器是一種 Gray 代碼計數器，它既生成 n 位 Gray 代碼序列 (見 3.2 節) 又生成 (n-1) 位 Gray 代碼序列。(n-1) 位 Gray 代碼是通過對 n-1 位 Gray 代碼的兩個 MSB 進行排斥或操作來生成的，以生成 (n-1) 位 Gray 代碼的 MSB。這與 n-1 位 Gray 代碼計數器的 (n-2) LSB 組合在一起，形成 (n-1) 位 Gray 代碼計數器 ^[5]。

3.4 其他Gary碼計數器注意事項（Additional Gray code counter considerations）

 The binary-value incrementer is conditioned with either an “if not full” or “if not empty” test as shown in Figure 3, to insure that the appropriate FIFO pointer will not increment during FIFO-full or FIFO-empty conditions that could lead to overflow or underflow of the FIFO buffer.If the logic block that sends data to the FIFO reliably stops sending data when a FIFO full condition is asserted, the FIFO design might be streamlined by removing the full-testing logic from the FIFO write pointer.The FIFO pointer itself does not protect the FIFO buffer from being overwritten, but additional conditioning logic could be added to the FIFO memory buffer to insure that a write_enable signal could not be activated during a FIFO full condition.An additional “sticky” status bit, either ovf (overflow) or unf (underflow), could be added to the pointer design to indicate that an additional FIFO write operation occurred during full or an additional FIFO read operation occurred during empty to indicate error conditions that could only be cleared during reset.A safe, general purpose FIFO design will include the above safeguards at the expense of a slightly larger and perhaps slower implementation. This is a good idea since a future co- worker might try to copy and reuse the code in another design without understanding all of the important details that were considered for the current design.

二進制計數器被條件化為 “如果不滿” 或 “如果不空” 測試，如圖 3 所示，以確保相應的 FIFO 指針在 FIFO 滿或 FIFO 空條件下不會增加（這些條件可能導致 FIFO 緩沖區溢出或下溢）。如果向 FIFO 發送數據的邏輯塊在斷言 FIFO 完整條件時可靠地停止發送數據，則可以通過從 FIFO write指針中刪除完整測試邏輯來簡化 FIFO 設計。FIFO 指針本身不能保護 FIFO 緩沖區免受覆蓋，但可以向 FIFO 內存緩沖區添加額外的條件化邏輯，以確保在 FIFO 完整條件下無法激活 write_enable 信號。可以在指針設計中添加一個額外的 “sticky” 狀態位( ovf (溢出) 或 unf (下溢)),指示在滿期間發生了額外的 FIFO 寫操作、或在空期間發生了額外的 FIFO 讀操作這些只能在reset期間清除的錯誤條件。一個安全、通用的 FIFO 設計將包含上述保障措施，但代價是一個稍大且可能更慢的實現。這是一個好主意，因為未來的復用者可能會試圖在另一個設計中復制和重用代碼，而不了解當前設計中考慮的所有重要細節。

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參考文獻：

《Simulation and Synthesis Techniques for Asynchronous FIFO Design》-- Clifford E. Cummings 

[1] Clifford E. Cummings, “Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs,” SNUG
2001 (Synopsys Users Group Conference, San Jose, CA, 2001) User Papers, March 2001, Section MC1, 3rd paper. Also
available at www.sunburst-design.com/papers
[2] Clifford E. Cummings and Don Mills, “Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever
know which to use?,” SNUG 2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers, March 2002,
Section TB2, 1st paper. Also available at www.sunburst-design.com/papers
[3] Clifford E. Cummings and Peter Alfke, “Simulation and Synthesis Techniques for Asynchronous FIFO Design with
Asynchronous Pointer Comparisons,” SNUG 2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers,
March 2002, Section TB2, 3rd paper. Also available at www.sunburst-design.com/papers
[4] Dinesh Tyagi, former CAE Manager for Synopsys DesignWare product, personal communication
[5] Edward Paluch, personal communication
[6] Frank Gray, "Pulse Code Communication." United States Patent Number 2,632,058. March 17, 1953.
[7] John O’Malley, Introduction to the Digital Computer, Holt, Rinehart and Winston, Inc., 1972, pg. 190.
[8] Steve Golson, personal communication
[9] Synopsys SolvNet, Doc Name: DesignWare-110.html, “Functional Bugs in DesignWare Components,” Updated:
11/30/2000