分享兩篇很棒的論文：

　　1.　《Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog》　

　　　　http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

　　2.　《Simulation and Synthesis Techniques for Asynchronous FIFO Design》

　　　　http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf